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PD - 95825 AUTOMOTIVE MOSFET IRLR024Z IRLU024Z HEXFET(R) Power MOSFET D Features n n n n n n Logic Level Advanced Process Technology Ultra Low On-Resistance 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax VDSS = 55V G S RDS(on) = 58m ID = 16A Description Specifically designed for Automotive applications, this HEXFET(R) Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. D-Pak IRLR024Z I-Pak IRLU024Z Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS (Thermally limited) EAS (Tested ) IAR EAR TJ TSTG Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Single Pulse Avalanche Energy Tested Value Avalanche Current Repetitive Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 16 11 64 35 0.23 16 25 21 See Fig.12a, 12b, 15, 16 -55 to + 175 Units A W W/C V mJ A mJ C 300 (1.6mm from case ) Thermal Resistance Parameter RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount) Junction-to-Ambient Typ. --- --- --- Max. 4.28 40 110 Units C/W HEXFET(R) is a registered trademark of International Rectifier. www.irf.com 1 3/10/04 IRLR/U024Z Electrical Characteristics @ TJ = 25C (unless otherwise specified) Parameter V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. Typ. Max. Units 55 --- --- --- --- 1.0 7.4 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.053 46 --- --- --- --- --- --- --- --- 6.6 1.6 3.9 8.2 43 19 16 4.5 7.5 380 62 39 180 50 81 --- --- 58 80 100 3.0 --- 20 250 200 -200 9.9 --- --- --- --- --- --- --- nH --- --- --- --- --- --- --- pF ns nC nA V S A V Conditions VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA VGS = 10V, ID = 9.6A m VGS = 5.0V, ID = 5.0A VGS = 4.5V, ID = 3.0A VDS = VGS, ID = 250A VDS = 25V, ID = 9.6A VDS = 55V, VGS = 0V VDS = 55V, VGS = 0V, TJ = 125C VGS = 16V VGS = -16V ID = 5.0A VDS = 44V VGS = 5.0V VDD = 28V ID = 5.0A RG = 28 VGS = 5.0V Between lead, 6mm (0.25in.) from package and center of die contact VGS = 0V VDS = 25V = 1.0MHz VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 44V, = 1.0MHz VGS = 0V, VDS = 0V to 44V G D S Source-Drain Ratings and Characteristics Parameter IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units --- --- --- --- --- --- --- --- 16 11 16 A 64 1.3 24 17 V ns nC Conditions MOSFET symbol showing the integral reverse G D S p-n junction diode. TJ = 25C, IS = 9.6A, VGS = 0V TJ = 25C, IF = 9.6A, VDD = 28V di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRLR/U024Z 100 TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V 100 TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 10 BOTTOM 10 BOTTOM 3.0V 1 1 3.0V 60s PULSE WIDTH 0.1 0.1 Tj = 25C 1 V DS, Drain-to-Source Voltage (V) 0.1 10 0.1 60s PULSE WIDTH Tj = 175C 1 V DS, Drain-to-Source Voltage (V) 10 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 15 Gfs, Forward Transconductance (S) ID , Drain-to-Source Current () T J = 175C 10 T J = 25C 10 TJ = 175C 5 V DS = 8.0V 300s PULSE WIDTH 0 0 2 4 6 8 10 12 14 16 ID,Drain-to-Source Current (A) 1 T J = 25C VDS = 10V 60s PULSE WIDTH 0 2 4 6 8 10 12 0.1 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current www.irf.com 3 IRLR/U024Z 10000 VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = C gd Coss = Cds + Cgd 6.0 5.0 4.0 3.0 2.0 1.0 0.0 ID= 5.0A VGS , Gate-to-Source Voltage (V) VDS = 44V VDS = 28V VDS = 11V C, Capacitance(pF) 1000 Ciss Coss Crss 100 10 1 10 100 0 1 2 3 4 5 6 7 VDS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 100 1000 OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 175C 10 ID , Drain-to-Source Current (A) ISD , Reverse Drain Current (A) 100 10 100sec 1 Tc = 25C Tj = 175C Single Pulse 0.1 1 10 T J = 25C VGS = 0V 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VSD, Source-to-Drain Voltage (V) 1msec 10msec 100 1000 VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U024Z 16 14 12 2.5 R DS(on) , Drain-to-Source On Resistance (Normalized) ID = 5.0A VGS = 5.0V 2.0 ID , Drain Current (A) 10 8 6 4 2 0 25 50 75 100 125 150 175 T C , Case Temperature (C) 1.5 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature (C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Normalized On-Resistance vs. Temperature 10 Thermal Response ( Z thJC ) D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE ) J R1 R1 J 1 2 R2 R2 C Ri (C/W) i (sec) 2.354 0.000354 1.926 0.001779 1 2 0.01 Ci= i/Ri Ci i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1 0.001 1E-006 1E-005 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U024Z 1 5V 100 EAS , Single Pulse Avalanche Energy (mJ) VDS L D R IV E R 80 ID 1.2A 1.8A BOTTOM 9.6A TOP RG VV 2 0GS D .U .T IA S tp 0 .0 1 + - VD D 60 A 40 Fig 12a. Unclamped Inductive Test Circuit V (B R )D SS tp 20 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) IAS Fig 12b. Unclamped Inductive Waveforms QG Fig 12c. Maximum Avalanche Energy vs. Drain Current 10 V QGS VG QGD VGS(th) Gate threshold Voltage (V) 2.5 2.0 Charge Fig 13a. Basic Gate Charge Waveform ID = 250A 1.5 L 0 DUT 1K VCC 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 TJ , Temperature ( C ) Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature 6 www.irf.com IRLR/U024Z 100 Avalanche Current (A) 10 Duty Cycle = Single Pulse 0.01 0.05 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses 1 0.1 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current vs.Pulsewidth 30 EAR , Avalanche Energy (mJ) 25 TOP Single Pulse BOTTOM 1% Duty Cycle ID = 9.6A 20 15 10 5 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = T/ ZthJC Iav = 2T/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Fig 16. Maximum Avalanche Energy vs. Temperature www.irf.com 7 IRLR/U024Z Driver Gate Drive D.U.T + P.W. Period D= P.W. Period VGS=10V + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt - - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs VDS VGS RG RD D.U.T. + -VDD 10V Pulse Width 1 s Duty Factor 0.1 % Fig 18a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr t d(off) tf Fig 18b. Switching Time Waveforms 8 www.irf.com IRLR/U024Z D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 6 .7 3 (.2 6 5 ) 6 .3 5 (.2 5 0 ) -A5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 1 .2 7 (.0 5 0 ) 0 .8 8 (.0 3 5 ) 2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 ) 1 .1 4 (.0 4 5 ) 0 .8 9 (.0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) 6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 6 .2 2 (.2 4 5 ) 5 .9 7 (.2 3 5 ) 1.0 2 (.0 4 0 ) 1.6 4 (.0 2 5 ) 1 2 3 0 .5 1 (.0 2 0 ) M IN . 1 0 .4 2 (.4 1 0 ) 9 .4 0 (.3 7 0 ) L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - S OU R CE 4 - D R A IN -B 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 3X 1 .1 4 (.0 4 5 ) 2X 0 .7 6 (.0 3 0 ) 2 .2 8 ( .0 9 0 ) 4 .5 7 ( .1 8 0 ) 0 .8 9 (.0 3 5 ) 0 .6 4 (.0 2 5 ) 0 .2 5 ( .0 1 0 ) M AMB N O TE S : 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) 1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0 .1 6 (.0 0 6 ) . D-Pak (TO-252AA) Part Marking Information Notes: T his part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRF R120 WIT H AS SEMBLY LOT CODE 9U1P INTERNAT IONAL RECT IF IER LOGO AS SEMBLY LOT CODE IRFU120 9U 016 1P DAT E CODE YEAR = 0 WEEK = 16 Notes: T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRF R120 WIT H AS SEMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN T HE ASS EMBLY LINE "A" PART NUMBER IRFU120 12 916A 34 INTERNAT IONAL RECT IF IER LOGO AS SEMBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A www.irf.com 9 IRLR/U024Z I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6 .7 3 (.26 5 ) 6 .3 5 (.25 0 ) -A 5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 1 -B 2.2 8 (.0 9 0) 1.9 1 (.0 7 5) 9 .6 5 ( .3 8 0 ) 8 .8 9 ( .3 5 0 ) 2 3 N O TE S : 1 D IM E N S IO N IN G & TO L E R A N C IN G P E R A N S I Y 1 4 .5M , 19 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R MS TO J E D E C O U T L IN E TO -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0.1 6 (.0 0 6 ). 6 .2 2 ( .2 4 5 ) 5 .9 7 ( .2 3 5 ) 1 .2 7 ( .0 5 0 ) 0 .8 8 ( .0 3 5 ) 2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - SOURCE 4 - D R A IN 3X 1 .1 4 (.0 45 ) 0 .7 6 (.0 30 ) 3X 0 .8 9 (.0 35 ) 0 .6 4 (.0 25 ) M AMB 1 .1 4 ( .0 4 5 ) 0 .8 9 ( .0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) 2 .28 (.0 9 0 ) 2X 0 .2 5 (.0 1 0 ) I-Pak (TO-251AA) Part Marking Information Notes : T his part marking information applies to devices produced before 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 9U1P INT ERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE DAT E CODE YEAR = 0 WEEK = 16 IRFU120 016 9U 1P Notes : T his part marking information applies to devices produced after 02/26/2001 EXAMPLE: T HIS IS AN IRFR120 WIT H AS SEMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN T HE ASS EMBLY LINE "A" INT ERNAT IONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A 10 www.irf.com IRLR/U024Z D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16 .3 ( .641 ) 15 .7 ( .619 ) 12.1 ( .47 6 ) 11.9 ( .46 9 ) F E E D D IR E C T IO N 8.1 ( .318 ) 7.9 ( .312 ) FE E D D IR E C T IO N N O T ES : 1 . C O N T R O LLIN G D IME N S IO N : M ILL IM ET E R . 2 . A LL D IM EN S IO N S A R E SH O W N IN M ILLIM ET E R S ( IN C H E S ). 3 . O U TL IN E C O N FO R MS T O E IA -481 & E IA -54 1. 1 3 IN C H 16 m m N O TE S : 1. O U TL IN E C O N F O R M S T O E IA -481 . Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by TJmax, starting TJ = 25C, L = 0.54mH RG = 25, IAS = 9.6A, VGS =10V. Part not recommended for use above this value. Pulse width 1.0ms; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. 100% tested to this value in production. When mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994. R is measured at TJ of approximately 90C. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 03/04 www.irf.com 11 |
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